simd.go

     1  // asmcheck
     2  
     3  // Copyright 2025 The Go Authors. All rights reserved.
     4  // Use of this source code is governed by a BSD-style
     5  // license that can be found in the LICENSE file.
     6  
     7  // These tests check code generation of simd peephole optimizations.
     8  
     9  //go:build goexperiment.simd && amd64
    10  
    11  package codegen
    12  
    13  import (
    14  	"math"
    15  	"simd/archsimd"
    16  )
    17  
    18  func vptest1() bool {
    19  	v1 := archsimd.LoadUint64x2([]uint64{0, 1})
    20  	v2 := archsimd.LoadUint64x2([]uint64{0, 0})
    21  	// amd64:`VPTEST (.*)(.*)$`
    22  	// amd64:`SETCS (.*)$`
    23  	return v1.AndNot(v2).IsZero()
    24  }
    25  
    26  func vptest2() bool {
    27  	v1 := archsimd.LoadUint64x2([]uint64{0, 1})
    28  	v2 := archsimd.LoadUint64x2([]uint64{0, 0})
    29  	// amd64:`VPTEST (.*)(.*)$`
    30  	// amd64:`SETEQ (.*)$`
    31  	return v1.And(v2).IsZero()
    32  }
    33  
    34  type Args2 struct {
    35  	V0 archsimd.Uint8x32
    36  	V1 archsimd.Uint8x32
    37  	x  string
    38  }
    39  
    40  //go:noinline
    41  func simdStructNoSpill(a Args2) archsimd.Uint8x32 {
    42  	// amd64:-`VMOVDQU .*$`
    43  	return a.V0.Xor(a.V1)
    44  }
    45  
    46  func simdStructWrapperNoSpill(a Args2) archsimd.Uint8x32 {
    47  	// amd64:-`VMOVDQU .*$`
    48  	a.x = "test"
    49  	return simdStructNoSpill(a)
    50  }
    51  
    52  //go:noinline
    53  func simdArrayNoSpill(a [1]Args2) archsimd.Uint8x32 {
    54  	// amd64:-`VMOVDQU .*$`
    55  	return a[0].V0.Xor(a[0].V1)
    56  }
    57  
    58  func simdArrayWrapperNoSpill(a [1]Args2) archsimd.Uint8x32 {
    59  	// amd64:-`VMOVDQU .*$`
    60  	a[0].x = "test"
    61  	return simdArrayNoSpill(a)
    62  }
    63  
    64  func simdFeatureGuardedMaskOpt() archsimd.Int16x16 {
    65  	var x, y archsimd.Int16x16
    66  	if archsimd.X86.AVX512() {
    67  		mask := archsimd.Mask16x16FromBits(5)
    68  		return x.Add(y).Masked(mask) // amd64:`VPADDW.Z .*$`
    69  	}
    70  	mask := archsimd.Mask16x16FromBits(5)
    71  	return x.Add(y).Masked(mask) // amd64:`VPAND .*$`
    72  }
    73  
    74  func simdMaskedMerge() archsimd.Int16x16 {
    75  	var x, y archsimd.Int16x16
    76  	if archsimd.X86.AVX512() {
    77  		mask := archsimd.Mask16x16FromBits(5)
    78  		return x.Add(y).Merge(x, mask) // amd64:-`VPBLENDVB .*$`
    79  	}
    80  	mask := archsimd.Mask16x16FromBits(5)
    81  	return x.Add(y).Merge(x, mask) // amd64:`VPBLENDVB .*$`
    82  }
    83  
    84  var nan = math.NaN()
    85  var floats64s = []float64{0, 1, 2, nan, 4, nan, 6, 7, 8, 9, 10, 11, nan, 13, 14, 15}
    86  var sinkInt64s = make([]int64, 100)
    87  
    88  func simdIsNaN() {
    89  	x := archsimd.LoadFloat64x4(floats64s)
    90  	y := archsimd.LoadFloat64x4(floats64s[4:])
    91  	a := x.IsNaN()
    92  	b := y.IsNaN()
    93  	// amd64:"VCMPPD [$]3," -"VPOR"
    94  	c := a.Or(b)
    95  	c.ToInt64x4().Store(sinkInt64s)
    96  }
    97  
    98  func simdIsNaN512() {
    99  	x := archsimd.LoadFloat64x8(floats64s)
   100  	y := archsimd.LoadFloat64x8(floats64s[8:])
   101  	a := x.IsNaN()
   102  	b := y.IsNaN()
   103  	// amd64:"VCMPPD [$]3," -"VPOR"
   104  	c := a.Or(b)
   105  	c.ToInt64x8().Store(sinkInt64s)
   106  }
   107  
   108  func sftImmVPSRL() archsimd.Uint32x4 {
   109  	var x archsimd.Uint32x4
   110  	// amd64:`VPSRLD \$1, .*$`
   111  	return x.ShiftAllRight(1)
   112  }
   113  
   114  func aLtbLtc8_avx512(a, b, c archsimd.Int8x64) archsimd.Mask8x64 {
   115  	// the vector length implies AVX512 implies the mask operations.
   116  	// amd64:`KANDQ`
   117  	return a.Less(b).And(b.Less(c))
   118  }
   119  
   120  func aLtbORbLtc8_avx512(a, b, c archsimd.Int8x64) archsimd.Mask8x64 {
   121  	// the vector length implies AVX512 implies the mask operations.
   122  	// amd64:`KORQ`
   123  	return a.Less(b).Or(b.Less(c))
   124  }
   125  
   126  func aLtbLtc64_avx512(a, b, c archsimd.Int64x8) archsimd.Mask64x8 {
   127  	// the vector length implies AVX512 implies the mask operations.
   128  	// amd64:`KANDB`
   129  	return a.Less(b).And(b.Less(c))
   130  }
   131  
   132  func aLtbORbLtc64_avx512(a, b, c archsimd.Int64x8) archsimd.Mask64x8 {
   133  	// the vector length implies AVX512 implies the mask operations.
   134  	// amd64:`KORB`
   135  	return a.Less(b).Or(b.Less(c))
   136  }
   137  
   138  var globalSlice = []uint32{1, 2, 3, 4, 5, 6, 7, 8}
   139  
   140  func simdMemoryOperandMerge() archsimd.Uint32x4 {
   141  	a := archsimd.BroadcastUint32x4(1)
   142  	// amd64:`VPADDD \([A-Z]+\), X\d, X\d`
   143  	a = a.Add(archsimd.LoadUint32x4(globalSlice[0:4]))
   144  	// amd64:`VPADDD 16\([A-Z]+\), X\d, X\d`
   145  	a = a.Add(archsimd.LoadUint32x4(globalSlice[4:8]))
   146  	return a
   147  }
   148
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